instruction decoder
英 [ɪnˈstrʌkʃn ˌdiːˈkəʊdə(r)]
美 [ɪnˈstrʌkʃn ˌdiːˈkoʊdər]
网络 指令译码器; 指令译码单元; 指令解码器; 译码器; 解码器
双语例句
- The interpretation is carried out by the instruction decoder.
该翻译借指令译码器来进行。 - CPU caches mark referenced memory as code or data depending upon whether it is sent to an instruction decoder.
CPU缓存像标记代码和数据一样标记被引用的内存，是依靠判断它是否被发送到指令解码器。 - Although they are not shown in this diagram, there would be control lines from the instruction decoder.
尽管图中没有显示，但指令译码器还有下列功能的控制线。 - Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle.
提出基于指令类型动态分配的译码器设计方案和基于指令执行周期的动态逻辑发射方案。 - During the test, some problems of the algorithm were found, and then an improved method was given and it removed the feature of instruction bundle, supplied a unique virtual address to each instruction on which the decoder acted.
根据测试中发现该算法存在的问题，提出了改进方案，消除束的特性，给每条指令赋予唯一地址并按此地址进行解码。 - The key of this design is the design of instructions state machine. Every instruction cycle includes 8 machine clock cycles, is made up of fetch instruction, decoder instruction, execute instruction, writing RAM, writing register and reading RAM etc.
本设计的关键点为指令执行状态级的设计，每个指令周期包括8个机器时钟周期，由取指、译指、执指、RAM读、寄存器写、RAM写等组成； - So research on how to design a suitable and effectual instruction decoder can speedup the instruction decoding, enhance the efficiency of the instruction pipeline, and consequently improve the performance of microprocessor effectively.
设计高效合理的译码器是加快指令译码速度，提高指令流水效率，进而有效提高处理器性能的重要保证。 - Design of Instruction Decoder Based on CPLD
基于CPLD的指令解码器设计 - Design of Instruction Decoder for Use in China for an Embedded MPU
一种嵌入式MPU指令译码器设计 - Design and Realization of Instruction Decoder;
指令译码器的设计； - Design of Instruction Decoder of Reconfigurable Embedded DSP Processor
嵌入式可重构DSP处理器的指令译码器设计 - The instruction decoder is designed to facilitate prioritized thread scheduling. The instruction issue logic considers the utilization of the shared execution pipeline. And the interface between direct memory access and scratch-pad memory is refined.
设计了有利于线程优先级调度的译码段，考虑了共享流水线资源利用率的指令发射逻辑和改进的直接存储访问和便签式存储器接口。 - Then use the multimedia instruction set that MMX technology on the decoder is optimized, mainly on the loop filter module is optimized.
最后又用多媒体指令集即MMX技术对环路滤波模块做了进一步的优化。